High speed electronic signals circuits place significant demands on the circuits and interconnections employed in their point-to-point transmission. This is becoming increasingly important as signal speeds enter the multi-gigahertz range. The challenge begins at the chip and from there the problems cascade through the entire electronic interconnection chain. Ultimately the transmission of electronic signals through signal paths of uniform impedance is critical to the performance of advanced systems. This being so, interconnecting devices and structures that provide such capability are vitally important to the production of viable electronic products. Unfortunately, properly controlling the characteristic impedance, while changing the feature sizes and spacing of the conductors and changing location to redistribute signals exiting the chip, is extremely challenging using current design practices.
Typically, traditional interconnection schemes, beginning at the chip, create small discontinuities at each interconnection transition. For example, while the chip design provides for internal control of the myriad of signal generating circuits within it, the next level interconnections, such as the wire bonds used to interconnect the chip to the package, typically begin the signal degradation process by creating both a small amount capacitance at the point of interconnection and excessive inductance which can cause cross talk. The length of the wire bond, at which point the concerns of inductance becomes critical, is determined by the frequency of the signals being transmitted. As signal speeds rise, the acceptable lead length must be shorter so as not to interfere with the signal. Further down the interconnection pathway, the circuit paths within the package may also contribute to the degradation as those signals are redistributed to make their escape from the package. From there, interconnections to the printed circuit board or next level interconnection devices may include sockets, connectors and other circuit boards. With signal integrity a key objective at high speed, any disruption of the signal in transmission goes counter to that objective and can result in signal degradation, loss and reflections. While a number of solutions are available for low pin counts ICs, owing to the short electrical path and the degrees of freedom associated with such low pin counts, as the pin counts rise, the number of solutions drops off rapidly.
Overcoming the problem for higher pin count applications in a cost effect way is an area of need for innovative solutions. More specifically, there is need for IC packaging and probe head solutions which provide an uninterrupted, controlled impedance path from the terminations on the IC die to the terminations either on a package or to a probe card which will serve to interconnect to the next level interconnection substrate or electrical test system.
Thus it is desirable to have an interconnecting structure that provides a substantially seamless transition from one signal pitch to another without disturbing signal quality. Structures and methods for accomplishing these objectives and other objectives are disclosed herein.